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CRUXOPEN
中文

Open silicon · Algorithm → RTL → Board

Open hardware,
verified bit for bit.

CruxOpen builds AI accelerators and image pipelines in the open: an executable golden model first, RTL that matches it on every byte, and a real FPGA board at the end.

See the projectsStart a conversation

Measured, not projected

Qwen3-0.6B decode on a KV260
0.07s/token
↳ openTARS README · Tested models (Qwen3-0.6B, KV260, 100 MHz)
Qwen3.5-0.8B vs golden model
Bit-exactevery logit, on board
↳ openTARS README · run.sh selftest on the board
openISP live camera pipeline
4K30on board
↳ openISP README · Hardware ISP on AMD Kria KV260
regression tests, plus 141 RTL mutants
748tests
↳ openTARS README · Run (pytest) + 141-mutant RTL mutation check

01 / Projects

Two open-source designs, both running on hardware.

Each repository holds the golden model, the RTL, the board build and the software that drives it.

LLM accelerator · NPU

openTARS

A single-core NPU that runs Qwen3.5-0.8B and Qwen3-0.6B on an off-the-shelf FPGA board, with every logit matching the golden model.

ModelDecodeModel image
Qwen3.5-0.8B0.13 s/tok887 MiB
Qwen3-0.6B0.07 s/tok662 MiB

On the board

Board
AMD Kria KV260 (XCK26)
Core clock
100 MHz
LUT use
90%
Weights
INT8 W8A8
Bitstream v1.0 → v3.3
2.6 → 0.13 s/token

How it is verified

  • Executable contract and golden model in Python, checked against transformers before any RTL
  • RTL vs golden, byte for byte: random queues, random stalls, five array shapes
  • 748 regression tests and a 141-mutant check: every injected RTL bug must be caught
  • Same core timed for ASIC: 1 GHz pre-layout on ASAP7

Honest numbers: MTP speculative decoding is implemented and bit-identical, but averages 0.97× on this hardware (break-even at 77% draft hits), so it ships off by default.

GitHub repository ↗Full demo video ↗Project log (Chinese) ↗
Qwen3.5-0.8B chatting on the KV260 through the openTARS NPU
Qwen3.5-0.8B · KV260 · bitstream v3.3
SystemVerilogVerilatorDRAMsim3VivadoYosys + ASAP7Python golden model

↳ Source: openTARS/README.md

Camera pipeline · ISP

openISP

A full image signal processor in SystemVerilog (no HLS), from RAW sensor input to a live HDMI preview, with hardware 3A statistics and its own tuning tool.

On the board

Sensor
onsemi AR1335
Video
1080p30 · 4K30
Measured
30.04 fps @ 4K
Video clock
200 MHz
Datapath
2 pixels/clock
Area
35% LUT (250 MHz OOC)

Full stack

RTL → AXI4-Lite control → V4L2 driver → AE/AWB/AF daemon → PC tuning tool

127 tests: model, RTL vs model, firmware vs model, tuning

Open items: ColorChecker colour calibration, 250 MHz video clock, NV12 output, lens shading.

GitHub repository ↗Bring-up notes ↗RTL documentation ↗
CSI-2 RAW in2 pixels/clock
  1. BayerDPCBLCAAFAWBCNFCFA
  2. RGBCCMGammaCSC
  3. YUVNLMBNFEEFCSHSCBCC
+ 3A statistics (AE · AWB · AF)YUYV → DDR → HDMI/DP
RTL blocks, bit-exact vs the integer model
SystemVerilog (no HLS)Verilator / xsimV4L2 driverAE/AWB/AF firmwarePC tuning tool

↳ Source: openISP/README.md · hw/kv260/README.md

02 / Method

The golden model is the source of truth.

  1. 01 · Contract

    Write the spec down

    A versioned contract fixes formats, numerics and reduction order. Ambiguity is decided on paper, not in RTL.

  2. 02 · Golden

    Make it executable

    A Python golden model implements the contract and is checked against the real reference (PyTorch / transformers) first.

  3. 03 · RTL

    Match it on every byte

    Random fuzzing, directed tie and corner vectors, and mutation testing until every injected bug is caught.

  4. 04 · Board

    Prove it on hardware

    The same check runs on the FPGA: the board's output is compared bit for bit with the golden model.

03 / Engineering notes

What the hardware taught us.

Short lessons from the project logs. Long-form articles are on the way.

openTARS

A GEMV is not a GEMM with M = 1

An output-stationary array uses one row at decode. A dot-product path at the port's 16 B/cycle made decode port-bound.

Read in the repo ↗openTARS

A DRAM model changes what is worth optimizing

A row interleave that was harmless on an ideal port cost 2.7× read amplification on LPDDR4X.

Read in the repo ↗openTARS

Random vectors almost never hit a rounding tie

A wrong rounding mode passed 200k random vectors. Constructed tie vectors caught it at once.

Read in the repo ↗openTARS

Why speculative decoding stays off

Each MTP round costs about 1.76 plain steps on this core, so it only pays above ~77% draft hits.

Read in the repo ↗

04 / Collaborate

Have a hardware problem worth solving?

Open to selected hardware projects, research collaborations and early-stage teams building AI or vision silicon.

Email us

hello@cruxopen.com

Tell us what you are building, where it runs, and what “done” looks like.

  • 01

    AI accelerator architecture

    Dataflow, memory hierarchy and roofline analysis for LLM and vision workloads on edge NPUs.

  • 02

    RTL design & verification

    Golden-model-driven RTL, bit-exact regression, fuzzing and mutation testing.

  • 03

    FPGA bring-up

    Kria / Zynq UltraScale+ block designs, Linux drivers and on-board validation.

  • 04

    ISP pipeline & tuning

    Bayer-to-YUV pipelines, 3A statistics, calibration and tuning tools.